“The enhancements in the latest release of Synopsys' Synplify synthesis software enable designers using our Stratix FPGAs to quickly complete their complex designs,” said Phil Simpson, senior manager of software technical marketing at Altera.
For ASIC prototypers, support for Synopsys DesignWare Library MacroCell IP has been added, broadening DesignWare IP support and improving compatibility with Design Compiler. Additionally, an enhanced interface for the tool allows designers to track progress and analyze synthesis results hierarchically. The new Synplify tool release enables engineers to build higher reliability into their FPGA designs through a new feature that provides automated creation and preservation of error-correction logic, including safe finite-state machines (FSMs).
#Synplify pro cost verification
Synopsys, a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced availability of the latest release of its Synplify Pro and Synplify Premier FPGA synthesis tools. In about 10 minutes I have to race down to the airport to catch a plane, so I am just going to post this press release as it is…
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